Field of the Invention
The present invention is related to data converters and more particularly to digital-to-analog converters.
Description of the Related Art
In general, a digital-to-time converter is a digital-to-analog data converter that generates an output signal having a period or edge delay based on a digital control word and a reference clock signal. For example, a clock divider circuit is a digital-to-time period converter that generates an output clock signal based on a reference clock signal and a digital control word indicating a divide ratio (e.g. an integer divide ratio or a fractional divide ratio). The analog output is the period of the output clock signal. The output clock period is based on the digital control word and the clock period of the reference clock signal. The output clock signal has a digitally-defined, full-scale range and a least-significant bit clock period.
A typical integer clock frequency divider is a digital-to-time period converter that generates an output clock signal having a period based on an integer multiplication of the input clock period and has a static and bounded quantization error and random jitter based on thermal noise. The fractional clock frequency divider is a dithering modulus clock frequency divider generating output clock signals having an average output clock period that is based on a fractional multiplication of the input clock period. A particular digital control word has an integer portion and a fractional portion. The dithering modulus clock divider provides a noise-shaped integer control signal to an integer clock divider that receives a reference clock signal. The noise-shaped integer control signal dithers between integer clock divider values causing the integer divider to generate an output clock signal having a period that, on average, is the target fractional clock period. The analog quantization error of the dithering noise-shaped integer control signal causes substantial deterministic jitter that dominates the jitter performance.
Digital-to-time period converters are used in clock synthesizer applications. Integer-based PLLs have been used extensively in clock multiplication applications that demand superior spurious performance. In order to generate fractional output frequencies, a prescaler digital-to-time converter (DivP) is used in the reference path of the PLL while a separate digital-to-time converter is used in the feedback path (DivN). In this way, the reference clock frequency can be multiplied by N/P. While this technique has proved useful in industry, the frequency resolution supported by the clock multiplier directly constrains the maximum achievable bandwidth to about fref/(10×P). As a result, the system is more dependent on voltage-controlled oscillator phase noise performance which can often translate into higher power consumption. In addition, the low loop bandwidth of the clock synthesizer reduces its usefulness in data communication applications to supporting significantly lower data rates than might otherwise be desired.
Referring to FIG. 1, an exemplary clock synthesizer utilizes phase-locked loop (PLL) 100, which includes a phase/frequency detector 102, a charge pump loop filter 104, and a voltage-controlled oscillator (VCO) 106. Voltage controlled oscillator 106 may be implemented as a ring oscillator, an LC oscillator, or other suitable oscillator structure. Phase/frequency detector 102 receives reference clock signal ckin, which may be provided by a fixed source, such as a crystal oscillator, a microelectromechanical structure (MEMS) oscillator, or other suitable source. Fractional divider 108 introduces a digital quantization error that causes phase noise (i.e., jitter) in the feedback clock signal, ckfb. For example, ckfb may have jitter of up to one cycle of the VCO output ckVCO.
A reference signal having a frequency fin supplied to PLL 100 is multiplied based on a divider value to generate a synthesized clock signal ckVCO. Frequency fout of the output clock signal, ckout, can be determined by a divider value Dfb of the feedback divider in the PLL, and in embodiments including output divider 110, a divider value Dout of output divider 110:
      f    out    =            f      in        ⁢                            D                      f            ⁢                                                  ⁢            b                                    D          out                    .      The feedback divider includes a digital-to-time converter that may be a fractional-N feedback divider 108 that receives clock signal ckVCO as the reference clock signal and digital control word Dfb. Digital control word Dfb is a divide value sequence of integers corresponding to a target fractional divider ratio. The synthesized clock signal ckVCO may be further divided by an output divider, which may be an integer clock divider including a digital-to-time period converter that generates the output clock signal ckout based on clock signal ckVCO as the reference clock signal and integer divide value Dout. In applications with demanding spur specifications, another integer clock divider (not shown) receives an input clock and a divide value Din and generates reference clock signal ckin provided to phase frequency detector 102. Note that in such embodiments an integer clock divider may be used instead of fractional divider 108 and Din, Dfb, and Dout have integer values to generate output clock signal ckout a signal having a frequency:
      f    out    =            f      in        ⁢                            D                      f            ⁢                                                  ⁢            b                                                D            in                    ⁢                      D            out                              .      However, an input integer divider provides frequency resolution at the expense of phase noise. Using a fractional-based digital word for Dfb and fractional divider 108 instead of an integer input divider and an integer feedback divider, supports higher output frequency resolution. The PLL behaves like a digital-to-analog converter reconstruction filter and reduces or eliminates high-frequency quantization noise. The higher PLL bandwidths improve VCO noise suppression but introduce deterministic jitter.
As the frequencies of ckin and ckout increase, the target clock period decreases and jitter introduced by the digital-to-time converter circuits become a larger fraction of the target clock period, thereby causing output clock signals from conventional clock synthesizer designs to fail to meet target performance specifications. Accordingly, improved techniques for digital-to-time conversion are desired.